In modern day communication systems, digital data is employed for transmission via a switching matrix to various subscribers associated with the system. The use of digital data enables efficient transmission and enables the various system modules to be implemented by integrated circuit techniques which are particularly well suited for the fabrication of digital circuitry.
In a digital telephone system, one converts analog or voice data to digital signals for processing and transmission via a switching matrix. The digital signals are converted back to analog signals to enable subscribers of the system to conventionally communicate. The digital telephony system enables one to implement subscriber line circuits mainly by employing digital circuitry which, as indicated, can be integrated as by LSI, large scale integrated circuits and hence, offers substantial reduction in costs and efficient and reliable operation.
The conversion of signals to analog or digital signals necessitates the use of both digital to analog converters and analog to digital converters. In any event, due to the cost considerations in any telephone systems, one must be concerned with economics as well as reliable operation consistent with modern day telephony requirements.
To implement analog to digital conversion, an analog signal is sampled at a high word rate, to provide digital words of a relatively small number of bits, each indicative of a weighted value of the analog signal. Such analog to digital converters (A/D) are referred to as "high-rate" devices and many suitable configurations are known.
In order to provide efficient transmission of the digital data obtained from a high rate converter, one must decimate (reduce) the word rate and increase the word length. This is done in the prior art by the use of digital filters designated as low pass devices to enable the high rate output signal to be decimated to a lower rate signal, which can be more readily handled and processed.
In any event, digital filters require multipliers, which are extremely expensive and complicated. For examples of such prior art filters, reference is made to U.S. Pat. No. 3,912,917 issued on Oct. 14, 1975 to H. Nussbaumer and entitled DIGITAL FILTER. This patent describes such filters and, in fact, attempts to reduce the number of multipliers required and hence, recognizes the problem associated with such devices.
Other patents as U.S. Pat. No. 4,021,654 issued on May 1, 1977 to H. H. Harris et al and entitled DIGITAL FILTER described filter embodiments used with LSI circuit techniques. Digital filters may also be accommodated by the use of computer circuits as evidenced by a recent article entitled "Implement Digital Filters Efficiently" by R. J. Karkowski and published in Electronic Design, Sept. 1, 1979, page 110 by Hayden Publishing Co.
Thus, it should be apparent that in a telephone system, which is an extensive communication transmission system, one must minimize hardware for both economic and reliability factors. Furthermore, in equipment employed in a telephone line circuit, costs and reliability are a prime factor as the line circuit is needed for each subscriber and hence, it is a system block which is repeated directly according to the number of subscribers.
While economics is a paramount concern, one must, of course, assure reliable and proper operation to afford to the subscriber the most optimum communications facilities.
The process of converting an analog signal to a digital signal in a high rate converter or in an A/D converter provides "quantizing" noise. In employing a high rate converter, such noise has a "high pass" spectrum and hence, as indicated, can be reduced by digital filtering. Thus, a decimator must attenuate the quantizing noise while decimating or decreasing the word rate, that is, by discarding data words such that the output word rate of the analog to digital converter, which is the input word rate of the decimator, is greater than the output word rate of the decimator by a factor of, for example, thirty two. The decimator is the dual of an interpolator, as the interpolator increases the word rate of a digital signal prior to performing a digital to analog (D/A) conversion, for example, by a factor of thirty two. Such interpolators are described in U.S. Pat. No. 4,109,110 entitled DIGITAL TO ANALOG CONVERTER issued on Aug. 22, 1978 to M. J. Gingell.
The problem of implementing a decimator function or an interpolator function while avoiding multipliers is applicable to both structures. The concepts and structure to be described herein are particularly adaptable for performing decimation and techniques for performing interpolation are described in a copending application entitled INTERPOLATOR APPARATUS FOR INCREASING THE WORD RATE OF A DIGITAL SIGNAL OF THE TYPE EMPLOYED IN DIGITAL TELEPHONE SYSTEMS by K. Shenoi et al and filed on Nov. 28, 1979 as Ser. No. 098,105, and assigned to the assignee herein.
While the use of a digital filter to provide a decreased output word rate is known, it must be of an economical and reliable configuration to accommodate the stringent cost and operation requirements associated with a telephone switching system. Thus, an object of this invention is to provide a decimator apparatus which reduces the output word rate of a high rate A/D converter, while eliminating the need for expensive hardware multipliers. The decimator apparatus further serves to reliably attenuate quantizing noise without interfering with the band of the analog signals (0-4 KHz) indicative of speech or voice signals. The decimator structure is easily implemented with conventional hardware and hence, enables the use of integrated circuit modules.
CL BRIEF DESCRIPTION OF PREFERRED EMBODIMENT
In accordance with this invention, the technique of reducing the word rate from a high input data word rate without introducing distortion by way of loss of essential information in the output words is described. In decimation, the number of bits/word is increased, for example, from 1-bit/word to 13-bits/word; and the word rate is decreased, for example, from 1.024 M word/sec to 32 K word/sec (a factor of 32).
A decimator apparatus for decreasing the word rate of an input digital signal, said input digital signal consisting of a plurality of digital words, each having the same number of given bits, with said rate of said digital signal being of a predetermined value fs comprising a cascaded digital filter arrangement having an input terminal and an output terminal, with, in a preferred embodiment a finite impulse response (FIR) filter is in cascade with and feeds a second order digital low pass recursive filter between said input and output terminals, said recursive filter characterized in having a transfer function defining filter coefficients to be of the form 2.sup.-K, where K is an integer to permit filtering of said input digital signal as applied to the input terminal of said cascaded arrangement, to provide at said output terminal an output filtered digital signal having a plurality of digital words, each of a greater number of bits than said input words and at a rate equal to said predetermined rate, and register means responsive to said output signal of said greater number of bit words for transferring said output signal at a lower rate than said predetermined rate, whereby said register means provides at an output, a decimated signal having a plurality of words each of a greater bit length than said input words and each manifesting the weighted value of said input words at a decreased word rate.